Paper-Conference

GadgetMeter: Quantitatively and Accurately Gauging the Exploitability of Speculative Gadgets
Since their emergence in 2018, speculative execution attacks have proven difficult to fully prevent without substantial performance …
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CiMSAT: Exploiting SAT Analysis to Attack Compute-in-Memory Architecture Defenses

Compute-in-memory (CiM) architecture is an emerging energyefficient processing paradigm that has attracted widespread attention in AI …
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TroScan: Enhancing on-chip delivery resilience to physical attack through frequency-triggered key generation
Keys grant access to devices and are the core secrets in logic obfuscation. Typically, keys are stored in tamper-proof memory and are …
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Securing Reset Operations in NISQ Quantum Computers
A secure reset operation could be an enabling technology that allows sharing of a quantum computer among different users, or among …
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Leaky Frontends: Micro-Op Cache and Processor Frontend Vulnerabilities
This paper evaluates new security threats due to the processor frontend in modern Intel processors. The root causes of the security …
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New Predictor-Based Attacks in Processors
The microarchitectural state held by predictors in modern processors can leak sensitive information. This is the first work to analyze …
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Device- and Locality-Specific Fingerprinting of Shared NISQ Quantum Computers
Fingerprinting of quantum computer devices is a new threat that poses a challenge to shared, cloud-based quantum computers. …
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Understanding Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities
This article discusses a recently developed test suite for checking timingbased vulnerabilities in processor caches, which has revealed …
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A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks
Based on improvements to an existing three-step model for cache timing-based attacks, this work presents 88 Strong types of theoretical …
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Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks
Many secure cache designs have been proposed in literature with the aim of mitigating different types of cache timing-based attacks. …
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