Paper-Conference

XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V
We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We …
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Secure TLBs
This paper focuses on a new attack vector in modern processors: the timing-based side and covert channel attacks due to the Translation …
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Cache timing side-channel vulnerability checking with computation tree logic
Caches are one of the key features of modern processors as they help to improve memory access timing through caching recently used …
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