THU-HAS Lab
THU-HAS Lab
Home
People
News
Publications
Join or Contact
Light
Dark
Automatic
Paper-Conference
TroScan: Enhancing on-chip delivery resilience to physical attack through frequency-triggered key generation
Keys grant access to devices and are the core secrets in logic obfuscation. Typically, keys are stored in tamper-proof memory and are …
Jianfeng Wang
,
Shuwen Deng
,
Huazhong Yang
,
Vijaykrishnan Narayanan
,
Xueqing Li
PDF
Securing Reset Operations in NISQ Quantum Computers
A secure reset operation could be an enabling technology that allows sharing of a quantum computer among different users, or among …
Allen Mi
,
Shuwen Deng
,
Jakub Szefer
PDF
Leaky Frontends: Micro-Op Cache and Processor Frontend Vulnerabilities
This paper evaluates new security threats due to the processor frontend in modern Intel processors. The root causes of the security …
Shuwen Deng
,
Wenjie Xiong
,
Jakub Szefer
PDF
New Predictor-Based Attacks in Processors
The microarchitectural state held by predictors in modern processors can leak sensitive information. This is the first work to analyze …
Shuwen Deng
,
Jakub Szefer
PDF
Device- and Locality-Specific Fingerprinting of Shared NISQ Quantum Computers
Fingerprinting of quantum computer devices is a new threat that poses a challenge to shared, cloud-based quantum computers. …
Allen Mi
,
Shuwen Deng
,
Jakub Szefer
PDF
Understanding Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities
This article discusses a recently developed test suite for checking timingbased vulnerabilities in processor caches, which has revealed …
Shuwen Deng
,
Wenjie Xiong
,
Jakub Szefer
PDF
A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks
Based on improvements to an existing three-step model for cache timing-based attacks, this work presents 88 Strong types of theoretical …
Shuwen Deng
,
Wenjie Xiong
,
Jakub Szefer
PDF
Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks
Many secure cache designs have been proposed in literature with the aim of mitigating different types of cache timing-based attacks. …
Shuwen Deng
,
Wenjie Xiong
,
Jakub Szefer
PDF
XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V
We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We …
Wen Wang
,
Bernhard Jungk
,
Julian Wälde
,
Shuwen Deng
,
Naina Gupta
,
Jakub Szefer
,
Ruben Niederhagen
PDF
Secure TLBs
This paper focuses on a new attack vector in modern processors: the timing-based side and covert channel attacks due to the Translation …
Shuwen Deng
,
Wenjie Xiong
,
Jakub Szefer
PDF
«
»
Cite
×