Paper-Conference

New Predictor-Based Attacks in Processors
The microarchitectural state held by predictors in modern processors can leak sensitive information. This is the first work to analyze …
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Device- and Locality-Specific Fingerprinting of Shared NISQ Quantum Computers
Fingerprinting of quantum computer devices is a new threat that poses a challenge to shared, cloud-based quantum computers. …
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Understanding Insecurity of Processor Caches Due to Cache Timing-Based Vulnerabilities
This article discusses a recently developed test suite for checking timingbased vulnerabilities in processor caches, which has revealed …
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A Benchmark Suite for Evaluating Caches’ Vulnerability to Timing Attacks
Based on improvements to an existing three-step model for cache timing-based attacks, this work presents 88 Strong types of theoretical …
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Analysis of Secure Caches using a Three-Step Model for Timing-Based Attacks
Many secure cache designs have been proposed in literature with the aim of mitigating different types of cache timing-based attacks. …
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XMSS and Embedded Systems - XMSS Hardware Accelerators for RISC-V
We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We …
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Secure TLBs
This paper focuses on a new attack vector in modern processors: the timing-based side and covert channel attacks due to the Translation …
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Cache timing side-channel vulnerability checking with computation tree logic
Caches are one of the key features of modern processors as they help to improve memory access timing through caching recently used …
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